eric

A dialog window in KiCad with a tree widget on the left showing a view of various rule categories with rules in them, the selected rule is "ignore_usb_silk_clearance" in the Manufacturability->Silk Clearance->Silk to silk clearance category. On the right side is a graphic explaining what silk to silk means and then a value of the clearance set to 0.00 mm. Under that are the conditions of the rule, it's for connector J1 and the Edge Cuts layer.

The new Design Rule Editor in @kicad.org nightly is looking good 😍

!!!! FINALLY !!!!!

You’re right, but the Bluesky post text is what is sensationalist. My bad.

Keep on with the both sides bad argument tho. That’s worked out real well 👍

NO IT DOES NOT. Holy fuck you people have no reading comprehension.

You’re legitimately arguing pointing out biased and bad reporting is bad? That’s no better than Fox News.

Just because it supports YOUR viewpoint doesn’t mean it’s not sensationalist.

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The entire point of this silly discussion is that Al Jazeera is no better than the NYP or Fox News for biased “reporting.” Stick to the AP.

They most certainly changed the headline which is what this entire thread is about (about mentioned several times, not the subtitle). The headline specifically mentioned Obama. Just bc Time Machine didn’t save the original doesn’t mean it didn’t exist.

Taking a break from a project to start* another 😅

Taking a break from one project to finish another, you mean? 😌

Reading comprehension please.

Btw, Al Jazeera changed the headline to more accurately reflect the article. So yes it was sensationalist.

Those two things are not mutually exclusive, holy shit. War crimes = bad. Sensationalist headline that is obviously biased = also bad.

Cat

>points out sensationalist headline
>instantly accused of supporting war crimes

You sound ridiculous honestly.

They’re doing the thing

Woohoo! 6 & 8 layer Aisler PCBs!

Wear a smart watch that vibrates?

(RPi FPGA SOC when?!)

I just got a RPi based logic analyzer that can sample at 200 MHz for a short period of time, so I guess it is possible. To your point though, processing will be the bottleneck

Resistance check rails before power on too!

I really enjoyed the circuits 2 lab for this reason where we actually built amps and other stuff

They spend all of 6 seconds explaining what a FET or BJT actually is (if you’re lucky) before jumping into small signal analysis for the next 3 lectures

The new bsky logo 🤮

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I did a pcie gen4 board two years ago which was cool, but relatively simple

I don’t really want to leave my job but I keep getting assigned less interesting boards to make (like a front panel board). The first real board I made here was the most advanced one I did, (18L, blind/buried vias) since then, like 4 years ago, it’s been not career-advancing stuff

ADDED: Ability to create flat-type schematics (ac8914e4) · Commits · KiCad / KiCad Source Code / kicad · GitLab Allows multiple, top-level schematic sheets. Records of the sheets are stored in the project file. All top-level sheets live under a virtual root sheet in the hierarchy. This virtual root...

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gitlab.com/kicad/code/k...