Myths Programmers Believe about CPU Caches As a computer engineer who has spent half a decade working with caches at Intel and Sun, I’ve learnt a thing or two about cache-coherency. This was one of the hardest concepts to learn back in coll…

“Myths Programmers Believe About CPU Caches” [2018], Rajiv Prabhakar (software.rajivprab.com/2018/04/29/m...).

Via HN: news.ycombinator.com/item?id=4576... & news.ycombinator.com/item?id=3633...

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cache-coherent – Chipress Posts about cache-coherent written by chipressian

We have compiled a series of posts on cache coherency during the past few months. Understanding cache coherency protocols is crucial in understanding how multi-threaded programs execute in a shared memory system. Check us out!

chipress.online/tag/cache-co...

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We (chipress.online/blog-posts/) have published several posts on cache coherence implementation with non-atomic operation handling. At school, such topics will be barely covered; but they are critical in real world implementation.

Check it out if you are interested!

#CacheCoherency #Cache #Atomic

Handling non-atomic requests in directory based MSI protocol (II) In the previous post, we discussed about handling non-atomic requests in directory based MSI protocol by stalls. In cache controller transient states such as “IS-D”, “IM-A” and “SM-A”, we could allow forwarded request messages to make progress without stalling, at the expense of adding more transient states. For example, when a cache controller has a line in State “IS-D” and receives an Inv message, it processes the request and changes the line’ state to “IS-D-I”, indicating the cache controller should change the line state to I after the “GetS” transaction completes.

In non-atomic requests handling in directory based MSI protocol, one can allow forwarded requests to make progress without stalling. Let's discuss how to achieve that in this post.

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Handling non-atomic requests in directory based MSI protocol (I) Just like snooping based protocols, directory based cache coherence protocol has to handle non-atomic requests in real world implementations. We start from the a directory based MSI base model, and discuss one solution on non-atomic requests handling. Base Model In directory based MSI protocol, there are 3 message types: Request messages, including GetS, GetM, PutM and PutS Forwarded request messages, including Fwd-GetS, Fwd-GetM, Inv (Invalidation), and Put-Ack…

In real world implementation of directory based MSI protocol, properly handling of non-atomic requests is required. Let's see how to achieve that (by stalls) in this post.

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Handling non-atomic operations in snooping based MSI protocol (II) In the previous post, we discussed non-zero delay from coherence requests to responses. However, coherence requests may also be non-atomic: a coherence request may not be instantly ordered when it is issued by a cache controller. For example, if there is a request queue between a cache controller and the system bus, coherence request atomicity is no longer guaranteed, and this is a fairly common implementation.

Implementing snooping based MSI protocol should consider non-atomic coherence requests as well. Let's see how address non-atomic coherence requests.

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Handling non-atomic operations in snooping based MSI protocol (I) In cache coherence protocol implementation, designers must properly handle non-atomic operations, since coherence transactions cannot complete instantly. We start from the well-known snooping based…

Handling non-atomic operations in snooping based MSI protocol (I) chipress.online/2025/07/25/h...

In real-world cache coherence implementation, designers must properly handle non-atomic operations. This is often overlooked, and we'll expand this topic in detail.

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Understand Cache Coherence from Memory Model’s Perspective To understand cache coherence, we have to take one step back and look at the memory model first. What is a Memory Model? Memory consistency model, or memory model, dictates the order in which memory reads and writes (or loads and stores) get applied to coherence shared memory systems. In the world of computer architecture, memory reads (or loads) permanently change processors’ …

To understand cache coherence, we have to take one step back and look at the memory model first.

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