#VTS2026 - IEEE VLSI Test Symposium 2026 program available; including our paper on "Automation of Polynomial Formal Verification using Large Language Models" tttc-vts.org/public_html/... @unibremen.bsky.social @dsc-ub.bsky.social @dfki.bsky.social #LLM #PolyVer #verification

#MBMV2026 - 29. Workshop zu Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen; program is #online; with three papers from @unibremen.bsky.social and @dsc-ub.bsky.social www.informatik.uni-wuerzburg.de/en/mbmv/prog... #PolyVer #CAUSE #explainability

Our paper in ACM Transactions on Design Automation of Electronic Systems ( #TODAES ) on "Linear Formal Verification of Sequential Circuits using Weighted-AIGs" is available #online as #OpenAccess dl.acm.org/doi/10.1145/... @unibremen.bsky.social @dfki.bsky.social #PolyVer #verification

#INCOWOCO2025 - giving a #keynote on "Polynomial Formal Verification: Towards Efficient and Provable System Design" at 2025 IEEE International Conference for Women in Computing incowoco.com/keynote/ @unibremen.bsky.social @dfki.bsky.social @dsc-ub.bsky.social #PolyVer #verification

Our paper in #ACM Transactions on Design Automation of Electronic Systems ( #TODAES ) on "Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity" is available #online as #OpenAccess dl.acm.org/doi/10.1145/... #PolyVer @unibremen.bsky.social #verification

#INCOWOCO2025 - looking forward to giving a #keynote on "Polynomial Formal Verification: Towards Efficient and Provable System Design" at 2025 IEEE International Conference for Women in Computing next week incowoco.com/keynote/ @unibremen.bsky.social @dfki.bsky.social #PolyVer #verification

#DTTIS2025 - Kamalika Datta and Lennart Weingarten from @unibremen.bsky.social and @dfki.bsky.social presenting our papers at #DTTIS dttis2025.uniwa.gr @dsc-ub.bsky.social #verification #synthesis #Plim #PolyVer

#DTTIS2025 - Lennart Weingarten from @unibremen.bsky.social presents our paper on "Towards Proofs for SCA-based Efficient Formal Verification of Complex Arithmetic Circuits" at #DTTIS dttis2025.uniwa.gr @dsc-ub.bsky.social @dfki.bsky.social #verification #formal #PolyVer

#DVConEurope2025 - today Lennart Weingarten from @unibremen.bsky.social presents on "Transformation-Aided Verification of MAC Designs using Symbolic Compute Algebra" at #DVConEurope; paper available #online at agra.informatik.uni-bremen.de/doc/konf/DVC... #verification #PolyVer @dfki.bsky.social

Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity | ACM Transactions on Design Automation of Electronic Systems In the field of Electronic Design Automation (EDA), managing circuit complexity is a crucial task for efficient circuit verification, testing, and optimization. Increasing design complexity presents c...

Our paper on "Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity" accepted for publication in ACM Transactions on Design Automation of Electronic Systems is now available #online as #OpenAccess dl.acm.org/doi/10.1145/... #PolyVer #verification @unibremen.bsky.social

#DSD2025 - Jan Kleinekathöfer from #AGRA @unibremen.bsky.social presenting our paper on "Automatic Polynomial Formal Verification of a Floating Point Multiplier" dsd-seaa.com/dsd2025/ @dsc-ub.bsky.social @dfki.bsky.social #PolyVer #verification

#FDL2025 - Rune Krauss from @dfki.bsky.social presenting our paper on "BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions" fdl-conference.com/program.html @dsc-ub.bsky.social @unibremen.bsky.social #PolyVer #verification #formal #FormalVerification #BDD #SAT

#FDL2025 - Lennart Weingarten from #AGRA @unibremen.bsky.social presenting our paper on "ForMAt: Formal Verification of Scalable Multiply and Accumulate Units" fdl-conference.com/program.html @dsc-ub.bsky.social @dfki.bsky.social #PolyVer #verification #formal #FormalVerification

#DSD2025 - Martha Schnieber from #AGRA @unibremen.bsky.social presenting our paper on "Synthesis for Testability: Polynomial Test Pattern Generation for KFDD Circuits"; paper is available #online agra.informatik.uni-bremen.de/doc/konf/DSD... @dsc-ub.bsky.social #PolyVer #testing #testability

Our paper in Microprocessors and Microsystems on "Polynomial formal verification parameterized by cutwidth properties of a circuit using Boolean satisfiability" is now available #online as #OpenAccess www.sciencedirect.com/science/arti... @unibremen.bsky.social @elsevierconnect.bsky.social #PolyVer

Für ihre Master-Arbeit mit dem Titel "Embedding Sequential Circuits for their Polynomial Formal Verification" wurde Caroline Dominik mit dem Fachbereichspreis #Informatik der @unibremen.bsky.social ausgezeichnet - herzlichen Glückwunsch! agra.informatik.uni-bremen.de/team_me.php?... #PolyVer

#ISDCS2025 - #keynote on "Towards LLM-based Generation of Human-Readable Proofs in Polynomial Formal Verification" at the 7th International Symposium on Devices, Circuits and Systems; paper is available on #arxiv arxiv.org/abs/2505.23311 @unibremen.bsky.social @dfki.bsky.social #LLM #LLMs #PolyVer

#ISDCS2025 - looking forward to giving a #keynote on "Towards LLM-based Generation of Human-Readable Proofs in Polynomial Formal Verification" at the 7th International Symposium on Devices, Circuits and Systems in #Kolkata, #India isdcs.iiests.ac.in @unibremen.bsky.social #verification #PolyVer

Our paper in the 2025 IEEE 26th Latin American Test Symposium (LATS) on "Preserving and Improving Verifiability of Circuits Based on Local Transformations" is available #online ieeexplore.ieee.org/abstract/doc... #LATS2025 @unibremen.bsky.social @dsc-ub.bsky.social #PolyVer #verification

Our paper in Information Processing Letters on "Lower bound proof for the size of BDDs representing a shifted addition" is available #online www.sciencedirect.com/science/arti... #PolyVer #verification #IPL

#DATE2025 - Mohamed Nadeem from @unibremen.bsky.social presents on "Polynomial Formal Verification of Sequential Circuits using Weighted-AIGs" agra.informatik.uni-bremen.de/doc/konf/DAT... #verification #FormalVerification #PolyVer #PolynomialFormalVerification @dfki.bsky.social

#DATE2025 - Lennart Weingarten from @unibremen.bsky.social presents on "Late Breaking Results: Towards Efficient Formal Verification of Dot Product" agra.informatik.uni-bremen.de/doc/konf/DAT... #verification #FormalVerification #PolyVer

#LATS2025 - #keynote at the 26th IEEE Latin American Test Symposium 2025, March 11-14, San Andrés Island, Colombia on "Preserving and Improving Verifiability of Circuits based on Local Transformations" cas.polito.it/LATS2025/pro... @unibremen.bsky.social #PolyVer #test #verification

Our paper in IEEE Transactions on Nanotechnology on "Polynomial Formal Verification of a RISC-V Processor" is available #online ieeexplore.ieee.org/document/109... @unibremen.bsky.social @dsc-ub.bsky.social #verification #PolynomialFormalVerification #PolyVer #riscv #risc @riscv.org.web.brid.gy

Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth Ensuring functional correctness is achieved through formal verification. As circuit complexity increases, limiting the upper bounds for time and space required for verification becomes crucial. Polyno...

Our paper in IEEE Transactions on Circuits and Systems I: Regular Papers on "Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth" is published in the March issue ieeexplore.ieee.org/document/108... @unibremen.bsky.social #PolyVer #verification

#LATS2025 - looking forward to deliver a #keynote at the 26th IEEE Latin American Test Symposium 2025, San Andrés Island, Colombia on "Preserving and Improving Verifiability of Circuits based on Local Transformations" cas.polito.it/LATS2025/pro... @unibremen.bsky.social @dfki.bsky.social #PolyVer

Automated polynomial formal verification using generalized binary decision diagram patterns | Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences With the ongoing digitization, digital circuits have become increasingly present in everyday life. However, as circuits can be faulty, their verification poses a challenging but essential challenge. I...

Our paper in Philosophical Transactions of the Royal Society on "Automated polynomial formal verification using generalized binary decision diagram patterns" now available royalsocietypublishing.org/doi/10.1098/... @unibremen.bsky.social #PolyVer #verification #PolynomialFormalVerification

Final version of our paper in Information Processing Letters on "Lower Bound Proof for the Size of BDDs representing a Shifted Addition" now available #online as #OpenAccess sciencedirect.com/science/arti... @unibremen.bsky.social #verification #PolyVer @elsevierconnect.bsky.social

Our paper in Information Processing Letters on "Lower Bound Proof for the Size of BDDs representing a Shifted Addition" is available #online www.sciencedirect.com/science/arti... @unibremen.bsky.social @dfki.bsky.social @dsc-ub.bsky.social #verification #PolyVer @elsevierconnect.bsky.social

Our paper in IEEE Transactions on Circuits and Systems I on "Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth" is available #online ieeexplore.ieee.org/document/108... @unibremen.bsky.social @dsc-ub.bsky.social @dfki.bsky.social #PolyVer #verification