For all the talk about covergroup inheritance in #systemverilog that one can find online since 2023, it seems that EDA vendors couldn't really be bothered to implement it.

DashRTL v2025.12 is now available for free trial:
dashthru.com/freetrial

#SystemVerilog #RTL #VLSI

ROHD A better way to develop hardware. Star Count

🚀 ROHD v0.6.7 is out!

This release focuses on cleaner generated RTL, better debugability, and faster simulation—plus lots of sharp edge-case fixes.

🔗 buff.ly/IuFHW8z

#ROHD #HardwareDesign #SystemVerilog #EDA #OpenSource

RE: https://tech.lgbt/@mlyoung/115825614845766367

Slingshot's graph-based indexing system is now fully functional and released! Give it a spin for yourself: github.com/mattyoung101/slingshot/r... :3

#systemverilog #lsp #foss

an extremely large GraphViz graph

closer up view of a GraphViz graph

Slingshot, my SystemVerilog LSP, is getting close to *full* dependency graph support as part of its indexing system! this will hopefully make indexing much faster and more stable in very large projects :blobcat:

here it is being tested with the Ibex RISC-V CPU:

#systemverilog #lsp

Desire: get some of my cool old vhdl and sv school projects working on blackice

Need: to review #UVM, but like idk I wanna play with FPGAs.

I should create a uvm testbench for one of my easier toy designs from school, perhaps.

I assume there are still no FOSS #systemverilog tools out, am I wrong?

EDA tool runtime too long? DashRTL is the ONLY solution that accelerates RTL analyze and elaborate with MULTI-CORE processing.
#VLSI #SystemVerilog #Verilog #RTL #HDL

Защитим вдов и сирот от хищных ИИ-стартаперов Ко мне на днях обратились сначала два стартапера, а потом и из ...

#SystemVerilog #Verilog #Electronic #Design #Automation #ChatGPT #Claude #deepseek #anthropic #AI #EDA

Origin | Interest | Match

Защитим вдов и сирот от хищных ИИ-стартаперов Ко мне на днях обратились сначала два стартапера, а потом и из ...

#AI #Anthropic #chatgpt #claude #deepseek #Electronic #Design #Automation #ml #SystemVerilog #Verilog

Origin | Interest | Match

ArteBirklaus - Twitch RISC-V Processor Design / DooM 2 =D

Circuit design on FPGA; "METAL MAGIC" stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch RISC-V Softcore Development

Circuit design on FPGA; "METAL MAGIC" stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch RISC-V processor design

Circuit design on FPGA; "METAL MAGIC" stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch Gamedev: Designing a RISC-V Processor

Circuit design on FPGA; "METAL MAGIC" stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch Gamedev: Designing a RISC-V CPU

Circuit design on FPGA; "METAL MAGIC" stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch I am an amateur game developer and computer-science student making my first serious attempt at creating a commercial game.

Circuit design on FPGA; "METAL MAGIC" stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch I am an amateur game developer and computer-science student making my first serious attempt at creating a commercial game.

METAL MAGIC stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch I am an amateur game developer and computer-science student making my first serious attempt at creating a commercial game.

METAL MAGIC stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch Magic Metal Monday

METAL MAGIC stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

How to Fail Those Students Who Rely on ChatGPT We at Verilog Meetup constructed an exam/interview...

habr.com/en/articles/905288/

#Wally #CPU #Verilog #SystemVerilog #Functional #Verification […]

[Original post on habr.com]

Как бороться с использованием ChatGPT студентами (не зап...

habr.com/ru/articles/902400/

#ChatGPT #Verilog #SystemVerilog #интервью #школа #синтеза #цифровых #схем #LLM #open #source

Result Details

Как бороться с использованием ChatGPT студентами Студен...

habr.com/ru/articles/902400/

#ChatGPT #Verilog #SystemVerilog #интервью #школа #синтеза #цифровых #схем #LLM #open #source

Result Details

Why do you use #verilog versus #VHDL versus #Systemverilog ?
I learned VHDL first on an #altera DE0-Nano as a hobby. then formally learn verilog on the realdigital blackboard( Xilinx Zynq SoC ) and now professionally program on #Xilinx Zynq ultrascale+ MPSoC.

ArteBirklaus - Twitch Geography & Softcores...

METAL MAGIC stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

ArteBirklaus - Twitch I am an amateur game developer and computer-science student making my first serious attempt at creating a commercial game.

METAL MAGIC stream starts now: www.twitch.tv/artebirklaus

#digitaldesign #systemverilog #vivado #fpga

Procedural Combinational Logic, SystemVerilog’s always_comb, and SSA in ROHD ROHD has recently gained a powerful new feature in the Combinational.ssa constructor for Combinationals that allows safer implementations of equivalent always_comb logic in SystemVerilog. This post…

It's pretty cool that my post on combinational logic in ROHD is in the top 3 results on Google when you search for `always_comb`! https://buff.ly/3Ek2XrY #rohd #always_comb #SystemVerilog #dart #opensource

#ASIC #RTL #Verilog #SystemVerilog #DV #EDA #Simulation #Testbench

#ASIC #RTL #Verilog #SystemVerilog #DV #EDA #Simulation #Testbench

#ASIC #RTL #Verilog #SystemVerilog #DV #EDA #Simulation #Testbench

#ASIC #RTL #Verilog #SystemVerilog #DV #EDA #Simulation #Testbench